Low Jitter, 10-output MEMS Jitter Cleaner
The SiT95145 is a single-chip MEMS jitter cleaner that provides the highest level of clock tree integration and consolidates multiple clock ICs and oscillators into a single device. Its low noise quad-PLL architecture and programmable output drivers provide up to 10 differential or 20 LVCMOS low-jitter clock outputs. It supports 4 additional clock inputs with Frac-N dividers, enabling virtually any input-to-output frequency translation configurations from 8 kHz to 2.1 GHz.
This jitter cleaner integrates SiTime’s third-generation MEMS resonator. This integrated MEMS approach eliminates the dependency on a crystal reference, along with all quartz related issues. It enables a true clock-system-on-a-chip that improves system robustness:
- Always-accurate clock synthesis by eliminating crystal capacitive mismatch
- Always-reliable startup even at cold temperature and other harsh environmental conditions
- No jitter degradation due to noise coupling onto a crystal interface
- No activity dips/frequency jumps inherent to quartz
- 10倍的抗振动和弯曲
The SiT95145 is supported by TimeMaster™ software to simplify clock tree design. The device can also be shipped with a user-specified, factory pre-programmed default startup configuration. The device configuration can be re-programmed twice using two banks of one-time-programmable (OTP) memory during manufacturing or configured in-system via I2C/SPI for additional BOM flexibility. The SiT95145 is also supported with theSiT6503EBevaluation board.
| Number of Inputs | 4 |
| Number of Outputs | 10 |
| Input Frequency Range | 8 kHz to 2.1 GHz (differential), 8 kHz to 250 MHz (LVCMOS |
| Output Frequency Range | 8 kHz to 2.1 GHz (differential), 8 kHz to 250 MHz (LVCMOS), 1 PPS (one output only) |
| Output Type | LVPECL, CML, HCSL, LVDS, LVCMOS |
| Number of PLL/Clock Domains | 4 PLL, 1 time domain |
| Programmable Loop Bandwidth | 1 mHz to 4 kHz |
| Operating Temperature Range (°C) | -40 to +85 |
| Phase Jitter (rms) | 120 fs |
| Voltage Supply (V) | 1.8, 2.5, 3.3 |
| Operating Mode | Free running, synchronized, holdover |
| Package Type (mm²) | 9x9 mm, 64-pin |
| Features | Hitless switching, zero-delay buffer mode, DCO with 50-ppt resolution, programmable output delay control |
| Availability | Sampling |
Single-chip MEMS jitter cleaner consolidates MEMS resonator, multiple clock ICs and oscillators into a single 9 x 9 mm 64-pin device
Clock-system-on-a-chip with integrated MEMS, simplifies designs
- No crystal capacity matching issues, always-accurate frequency synthesis
- No noise coupling onto crystal circuits, guaranteed jitter
- Resistant to vibration and board bending, anywhere PCB placement
Flexible features for the highest level of clock consolidation
- 4 inputs, 10 outputs, 4 PLLs, up to 2.1 GHz output frequency for flexible frequency translation
- Individually configurable output types and voltage to support a wide range of processor and SOCs
- Programmable loop bandwidth (1 mHz to 4 kHz)
35% space saving ideal for high density designs
- 9 x 9 mm package, no external XTAL/oscillator required
Semiconductor level quality and reliability, eliminating quartz related issues associated with traditional clocks
- Low jitter clock frequency translation and generation
- Clock tree consolidation replacing crystal oscillators (XOs) and buffers
- 10G/100G/400G Ethernet clocking
- Synchronous Ethernet (G.8262, options 1 and 2)
- Optical transport network (OTN) clocking for framers, mappers, and processors
- FPGA, processor, and memory clocking
- Storage, servers and datacenters
- 测量与测试
- Broadcast video
SiT6503EB Evaluation BoardUser Manual
TimeMaster for Clocks Software-- Simplifes clock tree design (Contact SiTime)