Differential oscillators are used in high performance applications and offer several benefits such as higher robustness to power supply noise. This application note provides termination recommendations for the SiTime differential oscillator families listed in Table 1, with LVPECL, LVDS, or HCSL output drivers. Interfaces for driving CML or HCSL clock inputs with LVPECL output are also discussed. Typical output rise and fall times of SiTime oscillators are in range of 250 ps to 600 ps, which causes even short traces on a PCB to behave like distributed transmission lines that require impedance matching. Therefore, it is recommended to design traces for differential signals as controlled impedance transmission lines with matched length. Those traces should be terminated properly for best signal integrity and lowest EMI. In addition to impedance matching, termination networks also impact DC bias and AC voltage swing at the receiver side.
